Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications

With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency

Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon

We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs

High Current Density Vertical Nanowire TFETs With I&#x2086;&#x2080; &#x003E; 1 <italic>&#x03BC;</italic>A/<italic>&#x03BC;</italic>m

We present experimental data for a vertical, 22-nm-diameter InAs/(In)GaAsSb nanowire Tunnel Field-Effect Transistor that exhibits the highest reported I60 of $1.2~\mu \text{A}/\mu \text{m}$ , paving the way for low power applications. The transistor reaches a minimum subthreshold swing of 43 mV/dec at $\text{V}_{DS}$ &#x003D; 300 mV with a sub-60 mV/dec operation over a wide current range. Combined with a high transconductance of $205~\mu \text{S}/\mu \text{m}$ , the ON-current for the same device is $18.6~\mu \text{A}/\mu \text{m}$ at $\text{V}_{DS}$ &#x003D; 300 mV for $\text{I}_{OFF}$ of 1 nA/ $\mu \text{m}$

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (g m,peak) by 50% among 28 devices and achieved 70 μS μm-1 at V DS = -0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec-1 as well as an off-current below 5 nA μm-1 which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device with L g = 80 nm in RTA, which shows an increased g m,peak up to 149 μS μm-1 at V DS = -0.5 V as well as a low on-resistance of 4.7 kΩ•μm. The potential of further enhancement in g m via RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications

Reconfigurable signal modulation in a ferroelectric tunnel field-effect transistor

Abstract Reconfigurable transistors are an emerging device technology adding new functionalities while lowering the circuit architecture complexity. However, most investigations focus on digital applications. Here, we demonstrate a single vertical nanowire ferroelectric tunnel field-effect transistor (ferro-TFET) that can modulate an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing with significant suppression of undesired harmonics for reconfigurable analogue applications. We realize this by a heterostructure design in which a gate/source overlapped channel enables nearly perfect parabolic transfer characteristics with robust negative transconductance. By using a ferroelectric gate oxide, our ferro-TFET is non-volatilely reconfigurable, enabling various modes of signal modulation. The ferro-TFET shows merits of reconfigurability, reduced footprint, and low supply voltage for signal modulation. This work provides the possibility for monolithic integration of both steep-slope TFETs and reconfigurable ferro-TFETs towards high-density, energy-efficient, and multifunctional digital/analogue hybrid circuits

Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S &lt; 100 mV/dec

III-V co-integration is less mature compared to Si/Ge CMOS due to their inferior pMOS device performance. This letter adopts a novel quaternary InGaAsSb channel material in a core-shell vertical nanowire structure to overcome the limitations. A gate-last process achieves self-alignment of the drain and gate contacts. The improved electrostatics with short gate length ${L}_{\text {g}}$ = 60 nm results in a good balance between the on-state and the off-state performances. The presented devices demonstrate the lowest inverse subthreshold slope ( ${S}$ ) for a III-V PMOS with ${S}_{\text {sat}}$ = 75 mV/dec with significant ${I}_{\text {on}}/{I}_{\text {off}}$ ratio of $10^{{4}}$ and ${I}_{\text {min}} <$ 1 nA/ $\mu \text{m}$. The substantial improvement in the device performance compared to earlier reports provides an opportunity for III-V complementary field-effect transistor integration

Sensing single domains and individual defects in scaled ferroelectrics

Ultra-scaled ferroelectrics are desirable for high-density nonvolatile memories and neuromorphic computing; however, for advanced applications, single domain dynamics and defect behavior need to be understood at scaled geometries. Here, we demonstrate the integration of a ferroelectric gate stack on a heterostructure tunnel field-effect transistor (TFET) with subthermionic operation. On the basis of the ultrashort effective channel created by the band-to-band tunneling process, the localized potential variations induced by single domains and individual defects are sensed without physical gate-length scaling required for conventional transistors. We electrically measure abrupt threshold voltage shifts and quantify the appearance of new individual defects activated by the ferroelectric switching. Our results show that ferroelectric films can be integrated on heterostructure devices and indicate that the intrinsic electrostatic control within ferroelectric TFETs provides the opportunity for ultrasensitive scale-free detection of single domains and defects in ultra-scaled ferroelectrics. Our approach opens a previously unidentified path for investigating the ultimate scaling limits of ferroelectronics

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si

Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III-V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III-V CMOS technologies

Compressively-strained GaSb nanowires with core-shell heterostructures

GaSb-based nanowires in a gate-all-around geometry are good candidates for binary p-type transistors, however they require the introduction of compressive strain to enhance the transport properties. Here, we for the first time demonstrate epitaxial GaSb-GaAsxSb1−x core-shell nanowires with a compressively strained core. Both axial and hydrostatic strain in GaSb core have been measured by X-ray diffraction (XRD) and Raman scattering, respectively. The optimal sample, almost without plastic relaxation, has an axial strain of −0.88% and a hydrostatic strain of −1.46%, leading to a noticeable effect where the light hole band is calculated to be 33.4 meV above the heavy hole band at the Γ-point. This valence band feature offers more light holes to contribute the transport process, and thus may provide enhanced hole mobility by reducing both the interband scattering and the hole effective mass. Our results show that lattice-mismatched epitaxial core-shell heterostructures of high quality can also be realized in the promising yet demanding GaSb-based system. [Figure not available: see fulltext.]